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class-d audio power amplifier adau1592 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features integrated stereo modulator and power stage 0.005% thd + n 101 db dynamic range psrr > 65 db r ds-on < 0.3 (per transistor) efficiency > 90% (8 ) emi-optimized modulator on/off-mute pop-noise suppression short-circuit protection overtemperature protection applications flat panel televisions pc audio systems mini-components general description the adau1592 is a 2-channel, bridge-tied load (btl) switching audio power amplifier with an integrated - modulator. the modulator accepts an analog input signal and generates a switching output to drive speakers directly. a digital, microcontroller-compatible interface provides control of reset, mute and pga gain as well as output signals for thermal and overcurrent error conditions. the output stage can operate from supply voltages ranging from 9 v to 18 v. the analog modulator and digital logic operate from a 3.3 v supply. functional block diagram a1 pvdd outl+ pgnd a2 b1 pvdd outl? pgnd b2 c1 pvdd outr+ pgnd c2 d1 pvdd outr? pgnd d2 level shift and dead time control - modulator temperature/ overcurrent protection mode control logic clock oscillator pga adau1592 f clk /2 voltage reference pga slicer ainl slc_th pga0 pga1 pga0 pga1 ainr vref avdd agnd dvdd dgnd otw xto xti err mute stdn mo/st 06749-001 figure 1.
adau1592 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 audio performance ...................................................................... 3 dc specifications ......................................................................... 4 power supplies .............................................................................. 4 digital i/o ..................................................................................... 4 digital timing............................................................................... 5 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 15 overview...................................................................................... 15 modulator.................................................................................... 15 slicer ............................................................................................. 15 power stage ................................................................................. 16 gain.............................................................................................. 16 protection circuits ..................................................................... 16 thermal protection.................................................................... 16 overcurrent protection ............................................................. 16 undervoltage protection ........................................................... 17 clock loss detection ................................................................. 17 automatic recovery from protections .................................... 17 mute and stdn ...................................................................... 17 power-up/power-down sequence .......................................... 18 dc offset and pop noise .......................................................... 19 selecting value for c ref and c in ............................................... 19 mono mode................................................................................. 19 power supply bypassing ............................................................ 19 external protection for pvdd > 15 v .................................... 20 clock ............................................................................................ 20 applications information .............................................................. 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 5/07revision 0: initial version
adau1592 rev. 0 | page 3 of 24 specifications avdd = 3.3 v, dvdd = 3.3 v, pvdd = 15 v, ambient temperature = 25c, load impedance = 6 , clock frequency = 24.576 mhz, measurement bandwidth = 20 hz to 20 khz, unless otherwise specified. audio performance table 1. parameter min typ max unit test conditions/comments output power 1 1 khz 12 w 1% thd + n, 8 15 w 10% thd + n , 8 14.5 w 1% thd + n, 6 18 w 10% thd + n, 6 19.5 w 1% thd + n , 4 24 w 10% thd + n , 4 efficiency 87 % @ 18 w, 6 r ds-on @ t case = 25c per high-side transistor 0.28 @ 100 ma per low-side transistor 0.25 @ 100 ma thermal characteristics thermal warning active 2 135 c die temperature thermal shutdown active 150 c die temperature overcurrent shutdown active 5 6 a peak current pvdd undervoltage shutdown 5.1 v input level for full-scale output full-scale output @ 1% thd + n 1.0 v rms pga gain = 0 db 0.5 v rms pga gain = 6 db 0.25 v rms pga gain = 12 db 0.125 v rms pga gain = 18 db total harmonic distortion + noise (thd+n) 0.005 % 1 khz, p out = 1 w, pga gain = 0 db signal-to-noise ratio (snr) 99 101 db a-weighted, referred to 1% thd + n output dynamic range (dnr) 99 101 db a-weighted, measured with ?60 dbfs input crosstalk (left to right or right to left) ?90 db @ full-scale output voltage, 1% thd + n, 1 khz amplifier gain pvdd = 15 v, 6 pga = 0 db 19 db pga = 6 db 25 db pga = 12 db 31 db pga = 18 db 37 db output noise voltage pvdd = 15 v, 6 pga = 0 db 78 v pga = 6 db 100 v pga = 12 db 158 v pga = 18 db 280 v power supply rejection ratio (psrr) 65 db 20 hz to 20 khz, 1.5 v p-p ripple, inputs ac-coupled to agnd 1 output powers above 12 w at 4 and above 18 w at 6 are not continuous and are thermally limited by the package dissipation. 2 thermal warning flag is for indication of device t j reaching close to shutdown temperature.
adau1592 rev. 0 | page 4 of 24 dc specifications table 2. parameter min typ max unit test conditions/comments input impedance 20 k ainl/ainr output dc offset voltage 3 mv power supplies table 3. parameter min typ max unit test conditions/comments analog supply voltage (avdd) 3.0 3.3 3.6 v digital supply voltage (dvdd) 3.0 3.3 3.6 v power transistor supply voltage (pvdd) 9 15 18 v power-down current stdn held low avdd 5 60 a dvdd 0.1 0.24 ma pvdd 0.082 0.25 ma mute current mute held low avdd 13 20 ma dvdd 1.7 3.2 ma pvdd 5.4 8 ma operating current stdn and mute held high, no input avdd 13 30 ma dvdd 2.7 4 ma pvdd 44 65 ma digital i/o table 4. parameter min typ max unit test conditions/comments input voltage input voltage high 2 v input voltage low 0.8 v output voltage output voltage high 2 v @ 2 ma output voltage low 0.4 v @ 2 ma leakage current on digital inputs 10 a
adau1592 rev. 0 | page 5 of 24 digital timing table 5. parameter min typ unit test conditions/comments t wait 0.01 1 1000 2 ms wait time for unmute t int 650 ms internal mute time t hold 10 1 250 3 s wait time for shutdown t outx+/outx? sw 200 s time delay after mute held high until output starts switching t outx+/outx? mute 200 s time delay after mute held low until output stops switching 1 t wait min and t hold min are the minimum times for fast turn-on and do not guarantee pop-and-click suppression. 2 t wait typ is the recommended value for minimum pop and click during the unmute of the amplifier. the recommended value is 1 sec. it is c alculated using the input coupling capacitor value and the input resistance of the device. see the power-up/power-down sequence section. 3 t hold typ is the recommended value for minimum pop an d click during the mute of the amplifier. 06749-002 stdn mute outx+/outx? t wait min internal mute notes 1. internal mute is internal to chip. t int t hold min figure 2 .timing diagram (minimum) 06749-003 notes 1. internal mute is internal to chip. stdn mute outx+/outx? t wait typ t hold typ internal mute t int t outx+/outx? sw t outx+/outx? mute figure 3. timing diagram (typical)
adau1592 rev. 0 | page 6 of 24 absolute maximum ratings table 6. parameter rating dvdd to dgnd ?0.3 v to +3.6 v avdd to agnd ?0.3 v to +3.6 v pvdd to pgnd 1 ?0.3 v to +20.0 v mute /stdn inputs dgnd ? 0.3 v to dvdd + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature soldering (10 sec) 260c vapor phase (60 sec) 215c infrared (15 sec) 220c 1 includes any induced voltage due to inductive load. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja 1 jc 1,2 jb jt unit lfcsp-48 24.6 2.0 8.05 0.18 c/w tqfp-48 24.7 1.63 11 0.8 c/w 1 with exposed pad (epad) soldered to 4-layer jedec standard pcb. 2 through the bottom (epad) surface. esd caution
adau1592 rev. 0 | page 7 of 24 pin configuration and fu nction descriptions 06749-004 13 14 15 16 17 18 19 20 21 22 23 24 pga1 pga0 mute stdn xti xto dgnd dvdd avdd agnd vref slc_th 48 47 46 45 44 43 42 41 40 39 38 37 pgnd pgnd pvdd pvdd pvdd pvdd pvdd pvdd pvdd pvdd pgnd pgnd 1 2 3 4 5 6 7 8 9 10 11 12 outl? outl? outl? outl+ outl+ outl+ test1 test0 otw mo/st test3 outr? outr? outr+ outr+ outr+ test13 test12 ainr ainl test9 test8 35 outr? 36 34 33 32 31 30 29 28 27 26 25 adau1592 top view (not to scale) pin 1 indicator err notes 1. epad not shown and internally connected to pgnd, dgnd, and agnd for tqfp-48. 2. epad not shown and internally connected to pgnd and dgnd for lfcsp-48. figure 4. pin configuration table 8. pin function descriptions pin number nemonic type 1 description 1, 2, 3 outl? o output of high power transistors, left channel negative polarity. 4, 5, 6 outl+ o output of high power transistors, left channel positive polarity. 7 test1 i reserved for internal use. connect to dgnd. 8 test0 i reserved for internal use. connect to dgnd. 9 err o error indicator (active low, open-drain output). 10 otw o overtemperature warning indicator (active low, open-drain output). 11 mo/st i mono/stereo mode setting pin for stereo. connect to dgnd (for mono mode, connect to dvdd). 12 test3 i reserved for internal use. connect to dvdd. 13 pga1 i programmable gain amplifier select, msb. 14 pga0 i programmable gain amplifier select, lsb. 15 mute i mute (active low input). 16 stdn i shutdown/reset input (active low input). 17 xti i quartz crystal connection/external clock input. 18 xto o quartz crystal connection/clock output. 19 dgnd p digital ground for digital circuitry. internally connected to exposed pad (epad). 20 dvdd p positive supply for digital circuitry. 21 avdd p positive supply for analog circuitry. (can be tied to dvdd.) 22 agnd p analog ground for analog circuitry. (see the notes in figure 4 for connection to epad.) 23 vref i avdd/2 voltage reference connection for external filter. 24 slc_th i slicer threshold adjust. (connect to agnd via a resistor for slicer operation.) 25 test8 i reserved for internal use. connect to dgnd. 26 test9 i reserved for internal use. connect to dgnd. 27 ainl i analog input left channel. 28 ainr i analog input right channel. 29 test12 i reserved for internal use. connect to dgnd. 30 test13 i reserved for internal use. connect to dgnd. 31, 32, 33 outr+ o output of high power transistors, right channel positive polarity.
adau1592 rev. 0 | page 8 of 24 pin number mnemonic type 1 description 34, 35, 36 outr? o output of high power tran sistors. right channel negative polarity. 37, 38, 47, 48 pgnd p power ground for high power transistors. internally connected to epad. 39, 40, 41, 42, 43, 44, 45, 46 pvdd p positive power supply for high power transistors. 1 i = input, o = output, p = power.
adau1592 rev. 0 | page 9 of 24 typical performance characteristics 06749-005 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 5. thd or thd + n vs. output power, 4 , pvdd = 9 v 0 6749-006 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 6. thd or thd + n vs. output power, 6 , pvdd = 9 v 06749-007 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 7. thd or thd + n vs. output power, 8 , pvdd = 9 v 06749-008 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 8. thd or thd + n vs. output power, 4 , pvdd = 12 v 06749-009 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 9. thd or thd + n vs. output power, 6 , pvdd = 12 v 0 6749-010 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 10. thd or thd + n vs. output power, 8 , pvdd = 12 v
adau1592 rev. 0 | page 10 of 24 06749-011 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 11. thd or thd + n vs. output power, 4 , pvdd = 15 v 06749-012 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 12. thd or thd + n vs. output power, 6 , pvdd = 15 v 0 6749-013 output power (w) thd or thd + n (db) ?120 0 ?10 ?20 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 thd + n thd figure 13. thd or thd + n vs. output power, 8 , pvdd = 15 v 0 6749-014 pvdd (v) output power (w) 0 30 25 5 10 15 20 618 89 71012 11 14 13 16 17 15 6 ? power limited due to package dissipation 4 ? 8 ? figure 14. output power vs. pvdd @ 0.1% thd + n 06749-015 pvdd (v) output power (w) 0 30 25 5 10 15 20 618 89 71012 11 14 13 16 17 15 6 ? 4 ? 8 ? power limited due to package dissipation figure 15. output power vs. pvdd @ 1% thd + n 06749-016 pvdd (v) output power (w) 0 40 35 5 10 15 20 618 89 71012 11 14 13 16 17 15 30 25 4 ? 8 ? 6 ? power limited due to package dissipation figure 16. output power vs. pvdd @ 10% thd + n
adau1592 rev. 0 | page 11 of 24 06749-017 frequency (khz) output (dbr) 0 ?160 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 220 4 6 8 1012141618 0dbr = 15w figure 17. fft @ 1 w, 6 , pvdd = 15 v, pga = 0 db, 1 khz sine 06749-018 frequency (khz) output (dbr) 0 ?160 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 220 4 6 8 1012141618 0dbr = 15w figure 18. fft @ ?60 dbfs, 6 , pvdd = 15 v, pga = 0 db, 1 khz sine 06749-019 frequency (khz) output (dbv) 0 ?140 0 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 220 4 6 8 1012141618 figure 19. fft no input, 6 , pvdd = 15 v, pga = 0 db 06749-020 frequency (khz) output (dbr) 0 ?160 0 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 222 20 4 6 8 1012141618 0dbr = 15w figure 20. fft @ 1 w, 6 , pvdd = 15 v, pga = 0 db, 19 khz and 20 khz sine 06749-021 frequency (hz) output (db) 20 ?120 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 1k 10k right to left left to right figure 21. crosstalk @ 1 w, 6 , pvdd = 15 v, pga = 0 db 06749-022 frequency (hz) output (db) 20 ?120 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 1k 10k right to left left to right figure 22. crosstalk @ full scale, 6 , pvdd = 15 v, pga = 0 db
adau1592 rev. 0 | page 12 of 24 0 6749-023 frequency (hz) thd or thd + n (db) ?120 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?20 ?10 ?30 20 10k 100 1k thd + n thd figure 23. thd or thd + n vs. frequency @ 1 w, 4 , pvdd = 15 v, pga = 0 db 0 6749-024 frequency (hz) thd or thd + n (db) ?120 ?20 ?10 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 20 10k 100 1k thd thd + n figure 24. thd or thd + n vs. frequency @ 1 w, 6 , pvdd = 15 v, pga = 0 db 0 6749-025 frequency (hz) thd or thd + n (db) ?120 ?20 ?10 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 20 10k 100 1k thd thd + n figure 25. thd or thd + n vs. frequency @ 1 w, 8 , pvdd = 15 v, pga = 0 db output (dbr) ?2.0 2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 20 100 1k 10k 06749-026 frequency (hz) figure 26. frequency response @ 1 w, 6 , pvdd = 15 v, pga = 0 db gain (db) 20 100 1k 10k 15 41 37 39 17 19 21 23 25 27 29 31 33 35 06749-027 frequency (hz) pga 18db pga 0db pga 6db pga 12db figure 27. gain vs. frequency @ 1 w, 6 , pvdd = 15 v 06749-028 ?100 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?90 ?10 psrr (db) 20 100 1k 10k frequency (hz) figure 28. psrr vs. frequency, no input signal, ripple = 1.5 v p-p, pvdd =15 v, 6
adau1592 rev. 0 | page 13 of 24 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 efficiency (%) 06749-029 output power (w) power limited due to package dissipation figure 29. efficiency vs. output power, 15 v, 4 0 10 20 30 40 50 60 70 80 100 90 0 5 10 15 20 25 efficiency (%) 06749-030 output power (w) power limited due to package dissipation figure 30. efficiency vs. output power, 15 v, 6 0 10 20 30 40 50 60 70 80 100 90 0 5 10 15 20 25 efficiency (%) 06749-031 output power (w) figure 31. efficiency vs. output power, 15 v, 8 0 1 2 3 4 5 6 7 8 12 9 10 11 0101525 20 power dissipation (w) 06749-032 output power per channel, stereo mode (w) 5 power limited due to package dissipation figure 32. power dissipati on vs. output power, 15 v, 4 , stereo mode, both channels driven power dissipation (w) 0 1 2 3 4 5 6 01525 10 20 06749-033 output power per channel, stereo mode (w) 5 power limited due to package dissipation figure 33. power dissipati on vs. output power, 15 v, 6 , stereo mode, both channels driven 0 1 4 2 3 power dissipation (w) 0 6749-034 output power per channel, stereo mode (w) 015 10 20 5 figure 34. power dissipati on vs. output power, 15 v, 8 , stereo mode, both channels driven
adau1592 rev. 0 | page 14 of 24 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 p diss max (w) 06749-035 t ambient (c) figure 35. power dissipation derating vs. ambient temperature 0 5 10 15 20 25 30 35 40 3 ? 06749-036 pvdd (v) output power (w) 918 12 11 14 13 16 15 6 ? 10 17 4 ? 8 ? power limited due to package dissipation figure 36. output power vs. pvdd, mono mode, 20 db thd + n 06749-037 pvdd (v) output power (w) 0 30 25 5 10 15 20 918 12 11 14 13 16 15 10 17 4 ? 3 ? 8 ? 6 ? power limited due to package dissipation figure 37. output power vs pvdd, mono mode, 40 db thd + n 06749-038 pvdd (v) output power (w) 0 30 25 5 10 15 20 918 12 11 14 13 16 15 10 17 4 ? 3 ? 8 ? 6 ? power limited due to package dissipation figure 38. output power vs. pvdd, mono mode, 60 db thd + n efficiency (%) 06749-039 output power (w) 0 10 20 30 40 50 60 70 80 90 0246810121416182022242628 36 34 32 30 power limited due to package dissipation figure 39. efficiency vs. output power, mono mode, 15 v, 3 efficiency (%) 06749-040 output power (w) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 10 20 30 40 50 60 70 80 90 figure 40. efficiency vs. output power, mono mode, 15 v, 4
adau1592 rev. 0 | page 15 of 24 theory of operation overview the adau1592 is a 2-channel high performance switching audio power amplifier. each of the two - modulators converts a single-ended analog input into a 2-level pdm output. this pdm pulse stream is output from the internal full differential power stage. the adau1592 has built-in circuits to suppress the turn-on and turn-off pop and click. the adau1592 also offers extensive thermal and overcurrent protection circuits. modulator the modulator is a 5 th -order - with feedback from the power stage connected internally. this helps reduce the external connections. the 5 th order modulator switches to a lower order near full-scale inputs. the modulator gain is optimized at 19 db for 15 v operation. the - modulator outputs a pulse density modulation (pdm) 1-bit stream, which does not produce distinct sharp peaks and harmonics in the am band like conventional fixed-frequency pwm. the - modulators require feedback to generate pdm stream with respect to the input. the feedback for the modulators comes from the power stage. this helps reduce the nonlinearity in the power stages and achieve excellent thd + n perform- ance. the feedback also helps in achieving good psrr. in the adau1592, the feedback from the power stage is internally connected. this helps reduce the external connections for ease in pcb layout. the - modulators operate in a discrete time domain and nyquist frequency limit, which is half the sampling frequency. the modulator uses the master clock of 12.288 mhz. this is generated by dividing the external clock input by 2. this sets the f s /2 around 6.144 mhz. this is sufficient for the audio bandwidth of 22 khz. the modulator shapes the quantization noise and transfers it outside the audio band. the noise floor rises sharply above 20 khz. this ensures very good signal-to- noise ratio (snr) in the audio band of 20 khz. the 6.144 mhz bandwidth allows the modulator order to be set around the 5 th order. the modulator uses proprietary dynamic hysteresis to reduce the switching rate or frequency to around 700 khz. this reduces the switching losses and achieves good efficiency. the dynamic hysteresis helps the modulator to continuously track the change in pvdd and the input level to keep the modulator stable. slicer the adau1592 has a built-in slicer block following the pga and before the modulator. the slicer block is essentially a hard limiter included for limiting the input signal to the modulator. this, in turn, limits the output power at a given supply voltage. the slicer in the adau1592 is normally inactive at lower input levels but is activated as soon as the peak input voltage exceeds the set threshold. the threshold can be set externally by connecting a resistor from slc_th (pin 24) to ground. this feature allows the user to adjust the slicer to the desired value and to limit the output power. for input signals higher than the set threshold, the slicer clips the input signal to the modulator. this adds distortion due to clipping of the signal input to the modulator. this is especially helpful in applications where the output power available needs to be reduced instead of reducing the supply voltage. figure 41 is a plot showing thd + n vs. the input level at 0 db pga, 15 v, and 6 , and demonstrates the difference between a device with and without the slicer. ?100 0 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 02.0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.2 thd + n (db) 06749-041 input (v rms) slicer 1.1v slicer 1.17v slicer 1.24v slicer 1.32v slicer disabled figure 41. thd + n vs. input level @ pga = 0 db, 15 v figure 42 depicts the typical output power vs input at different slicer settings. 0 25 5 10 15 20 02.0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.2 output power (w) 0 6749-042 input (v rms) slicer disabled slicer 1.32v slicer 1.24v slicer 1.17v slicer 1.10v figure 42. typical output power vs. input, at different slicer settings from figure 42, it can be seen that the slicer effectively reduces the output power depending on its setting. internally, the slicer block receives the input from the pga. figure 43 shows the block for slicer threshold adjust, slc_th (pin 24).
adau1592 rev. 0 | page 16 of 24 06749-043 v cm slicer_level 50k ? v th pin 24 (slc_th) r external figure 43. block for slicer threshold adjust, slc_th the slicer threshold can be set externally using a resistor as follows: v th = ( avdd /2) (50 k/50 k + r external ) where: av d d = 3.3 v typical. v th is the voltage threshold at which the slicer is activated. the following equation can be used to calculate the input signal at which the slicer becomes active: 0.9 1.414 = th in rms v v therefore, for av d d = 3.3 v typical and v th = 1.1 v, r external = 24.9 k v in rms = 0.864 v thus, the slicer is activated at and above 0.864 v in rms . this feature allows the user to set the slicer and, in turn, reduces the output power at a given supply voltage.to disable the slicer, slc_th should be connected to agnd. table 9 shows the typical values for r external . table 9. typical r external values v th (v) r external (k) v in rms (v) 1.1 24.9 0.864 1.17 20.5 0.919 1.24 16.5 0.974 1.32 12.4 1.037 power stage the adau1592 power stage comprises a high-side pmos and a low-side nmos. the typical r ds-on is ~ 300 m. the pmos- nmos stage does not need an external bootstrap capacitor and simplifies the high-side driver design. the power stage also has comprehensive protection circuits to detect the faults in typical applications. see the protection circuits section for further details. gain the gain of the amplifier is set internally using feedback resistors optimized for 15 v no minal operation. the typical gain values are tabulated in table 1. the typical gain is 19 db with pga set to 0 db. pga0 (pin 14) and pga1 (pin 13) are used for setting the desired gain. the gain can be set according to table 10. note that the ampli- fier full-scale input level changes as per the pga gain setting. table 10. gain settings pga1 (pin 13) pga0 (pin 14) pga gain (db) amplifier gain (db) full-scale input level (v rms ) 0 0 0 19 1 0 1 6 25 0.5 1 0 12 31 0.25 1 1 18 37 0.125 protection circuits the adau1592 includes comprehensive protection circuits. it includes thermal warning, thermal overheat, and overcurrent or short-circuit protection on the outputs. the err and otw outputs are open drain and require external pull-up resistors. the outputs are capable of sinking 10 ma. the open-drain outputs are useful in multichannel applications where more than one adau1592 is used. the error outputs of multiple adau1592s can be ored to simplify the system design. the logic outputs of the error flags ease the system design of using a microcontroller. thermal protection thermal protection in the adau1592 is categorized into two error flags: one as thermal warning and the other as thermal shutdown. when the device junction temperature reaches near 135c (5c), the adau1592 outputs a thermal warning error flag by pulling otw (pin 10) low. this flag can be used by the microcontroller in the system for indication to the user or can be used to lower the input level to the amplifier to prevent thermal shutdown. the device continues operation until shutdown temperature is reached. when the device junction temperature exceeds 150c, the device outputs an error flag by pulling err (pin 9) low. this error flag is latched. to restore the operation, mute (pin 15) needs to be toggled to low and then to high again. overcurrent protection the overcurrent protection in the adau1592 is set internally at a 5 a peak output current. the device protects the output devices against excessive output current by pulling err (pin 9) low. this error flag is latched. to restore the normal operation, mute (pin 15) needs to be toggled to low and then to high again. the error flag is useful for the microcontroller in the system to indicate abnormal operation and to initiate the audio mute sequence. the device senses the short-circuit condition on the outputs after the lc filter. typical short-circuit condi- tions include shorting of the output load and shorting to either pvdd or pgnd.
adau1592 rev. 0 | page 17 of 24 undervoltage protection the adau1592 is also comprised of an undervoltage protec- tion circuit, which senses the undervoltage on pvdd. when the pvdd supply goes below the operating threshold, the output fets are turned to a high-z condition. in addition, the device issues an error flag by pulling err low. this condition is latched. to restore the operation, mute (pin 15) needs to be toggled to low and then to high again. clock loss detection the adau1592 includes a clock loss detection circuit. in case the master clock to the part is lost, the err flag is set. this condition is latched. to restore operation, mute needs to be toggled low and high again. automatic recovery from protections in certain applications, it is desired for the amplifier to recover itself from thermal protection without the need for system microcontroller intervention. the adau1592 thermal protection circuit issues two error signals for this purpose: one a thermal warning ( otw ) and the other a thermal shutdown ( err ). with the two error signals, there are two options available for using the protections: ? option 1: using otw ? option 2: using err the following sections provide further details of these two options. option 1: using otw the otw pin is pulled low when the die temperature reaches 130c to 135c. this pin can be wired to mute as shown in figure 44, using an rc circuit. 06749-044 adau1592 otw to mute logic input d1 1n4148 dvdd r1 100k ? 10 15 mute c1 47f figure 44. option 1 schematic for autorecovery the low logic level on otw also pulls down the mute pin. the bridge is shut down and starts cooling or the die tempera- ture starts reducing. when it reaches around 120c, the otw signal starts going high. while this pin is tied to a capacitor with a resistor pulled to dvdd, the voltage on this pin starts rising slowly towards dvdd. when it reaches the cmos threshold, mute is deasserted and the amplifier starts functioning again. this cycle repeats itself depending on the input signal conditions and the temperature of the die. this option allows device operation that is safely below the shutdown temperature of 150c and allows the amplifier to recover itself without the need for microcontroller intervention. option 2: using err option 2 is similar to option 1 except the err pin is tied to mute instead of otw . see the circuit in figure 45. 06749-045 a dau1592 err to mute logic input d1 1n4148 dvdd r1 100k ? mute c1 47f 9 15 figure 45. option 2 schematic for autorecovery in this case, the part goes into shutdown mode due to any of the error generating events like output overcurrent, overtempera- ture, missing pvdd or dvdd, or clock loss. the part recovers itself based on the same circuit operation in figure 44. however, if the part goes into error mode due to overtempera- ture, then the device would have reached its maximum limit of 150c (15c to 20c higher than option 1). if it goes into error mode due to an overcurrent from a short circuit on the speaker outputs, then the part keeps itself recycling on and off until the short circuit is removed. it is possible that, with this operation, the part is subjected to a much higher temperature and current stress continuously. this, in turn, reduces the parts reliability in the long term. therefore, using option 1 for autorecovery from thermal protection and using the system microcontroller to indicate to the user of an error condition is recommended. mute and stdn the mute and stdn pins are 3.3 v logic-compatible inputs used to control the turn-on/turn-off for adau1592. the stdn input is active low when the stdn pin is pulled low and the device is in its energy saving mode. the modulator is inactive and the power stage is in high-z state. the high logic level input on the stdn pin wakes up the device. the modula- tor is running internally but the power stage is still in high-z state. when the mute pin is pulled high, the power stage becomes active with a soft turn-on to avoid the pop and clicks. the low level on the mute pin disables the power stage and is recommended to be used to mute the audio output. see the power-up/power-down sequence section for more details.
adau1592 rev. 0 | page 18 of 24 power-up/power-down sequence figure 46 shows the recommended power-up sequence for the adau1592. 06749-046 avdd/dvdd pvdd stdn mute outx+/outx? pvdd/2 ainx avdd/2 t pdl-h t int t wait t int = 650ms @ 24.576mhz clock t pdl-h = 200s t wait = 10 r in c in internal mute notes 1. internal mute is internal to chip. figure 46. recommended power-up sequence the adau1592 has a special turn-on sequence that consists of a fixed internal mute time during which the power stage does not start switching. this internal mute time depends on the master clock frequency and is 650 ms for a 24.576 mhz clock. also, the internal mute overrides the external mute and ensures that the power stage does not switch on immediately even if the external mute signal is pulled high in less than 650 ms after stdn . the power stage starts switching only after 650 ms plus a small propagation delay of 200 s has elapsed and after mute is deasserted. therefore, it is recommended to ensure that t wa i t > t int to prevent the pop and click during power-on. ensure that the mute signal is delayed by at least t wa i t seconds after stdn . this time is approximately 10 times the charging time constant of the input coupling capacitor. for example, if the input coupling capacitor is 4.7 f, the time constant is t = r c = 20 k 4.7 f = 94 ms therefore, t wa i t = 10 t = 940 ms ~ 1 sec. t wa i t is needed to ensure that the input capacitors are charged to avdd/2 b efore tur ning on t he p ower st age. when t wa i t < t int , the power stage does not start switching until 650 ms has elapsed after stdn (see figure 47). however, note that this method does not ensure pop-and-click suppression because of less than recommended or insufficient t wa i t t int = 650ms @ 24.576mhz clock t wait < t int 06749-047 a vdd/dvdd pvdd s tdn mute outx+/outx? pvdd/2 a inx avdd/2 t int t wait internal mute notes 1. internal mute is internal to chip. figure 47. power-up sequence, t wait < t int the adau1592 uses three separate supplies: avdd (3.3 v analog for pga and modulator), dvdd (3.3 v digital for control logic and clock oscillator), and pvdd (9 v to 18 v power stage and level shifter). separate pins are provided for the avdd, dvdd, and pvdd supply connections, as well as agnd, dgnd, and pgnd. in addition, the adau1592 incorporates a built-in undervolt- age lockout logic on dvdd as well as pvdd. this helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. the adau1592 monitors the dvdd and pvdd supply voltages and prevents the power stage from turning on if either of the supplies are not present or are below the operating threshold. therefore, if dvdd is missing or below the operating thresh- old, for example, the power stage does not turn on, even if pvdd is present, or vice versa. because this protection is only present on dvdd and pvdd and not on avdd, shorting both avdd and dvdd externally or generating avdd and dvdd from one power source is recommended. this ensures that both avdd and dvdd supplies are tracking each other and avoids the need to monitor the sequence with respect to pvdd. this also ensures minimal pop and click during power-up. when using separate avdd and dvdd supplies, ensure that both supplies are stable before unmuting or turning on the power stage. similarly, during shutdown, pulling mute to logic low before pulling stdn down is recommended. however, where a fault event occurs, the power stage shuts down to protect the part. in this case, depending on the signal level, there is some pop at the speaker.
adau1592 rev. 0 | page 19 of 24 to shut down the power supplies, it is highly recommended to mute the amplifier before shutting down any of the supplies. after mute is shut down, shut down the supplies in the following order: pvdd, dvdd, then avdd. where avdd and dvdd are generated from a single source, turn pvdd off before dvdd and avdd, and after issuing mute . dc offset and pop noise this section describes the cause of dc offset and pop noise during turn-on/turn-off. the turn-on/turn-off pop in amplifiers depend mainly on the dc offset, therefore, care must be taken to reduce the dc offset at the output. the first stage of adau1592 has an inverting pga amplifier, as shown in figure 48. 0 6749-048 changes with pga setting r fb to next stage ainx v ref c ref r in r source v mis c in figure 48. input equivalent circuit where: r in = 20 k, fixed internally. r fb is the gain feedback resistor (value depends on the pga setting). r source is the source resistance. c in is the input coupling capacitor (2.2 f typical) c ref is the filter capacitor for v ref . v ref is the analog reference voltage (avdd/2 typical). v mis is the dc offset due to mismatch in the op amp. as shown in figure 48, the dc offset at the output can be due to v mis (the dc offset from mismatch in the op amp) and due to leakage current of the c in capacitor. normally, the offset due to leakage current in the c in is less and can be ignored compared to v mis . the v mis is mainly responsi- ble for the dc offset at the output. the adau1592 uses special self-calibration or a dc offset trim circuit, which controls the dc offset (due to v mis ) to within 3 mv. the v mis can vary for each part as well as for voltage and temperature. the trim circuit ensures that the offset is limited within specified limits and provides virtually pop-free operation every time the part is turned on. however, care must be taken while unmuting or during the power-up sequence. during the initial power-up, c in and c ref are charging to avdd/2 and, during this time, there can be dc offset at the output (see figure 48). this depends on the pga gain setting. the dc offset is multiplied by the pga gain setting. if the amplifier is kept in mute during this charging and self- trimming event for the recommended t wa i t time, the dc offset at the output remains within 3 mv. for more details on t wa i t , refer to the power-up/power-down sequence section. the amount of pop at the turn-on depends on t wa i t , which in turn depends on the values of c ref and c in . the following section describes how to select the value for the c ref and c in . selecting value for c ref and c in the c ref is the capacitor used for filtering the noise from avdd on v ref . v ref is used for the biasing of the internal analog amplifier as well as the modulator. therefore, care must be taken to ensure that the recommended minimum value is used. the minimum recommended value for c ref is 4.7 f. c in is the input coupling capacitor and is used to decouple the inputs from the external dc. the c in value determines the low corner frequency of the amplifier. it can be determined from the following equation: in in low c r f = 2 1 where: f low is the low corner frequency (?3 db). r in is the input resistance (20 k). c in is the input coupling capacitor. note that r in = 20 k, provided that r source is <1 k. if r source is sizable with respect to r in , it also must be taken into account in calculation. from the preceding equation, f low can be found for the desired frequency response. the recommended value for c in is 2.2 f, giving f low = 3.6 hz and should keep 20 hz roll-off within ?0.5 db. however, if a higher than recommended c in value is used for better low frequency response, care must be taken to ensure that appropriate t wa i t is used. see the power-up/power-down sequence section for more details. mono mode the adau1592 mono mode can be enabled by pulling mo/ st (pin 11) to logic high. in this mode, the left channel input and modulator is active and feeds pwm data to both the left and right power stages. however, the respective power fets need to be connected externally for higher current capability. that is, connect outl+ with outr+ and outl? with outr?. the mono mode gives the capability to drive lower impedance loads without invoking current limit. however, the output power is limited by pvdd and temperature limits. see the typical applica- tion schematic in figure 50 for details. power supply bypassing because class-d amplifiers utilize high frequency switching, care must be taken to bypassing the power supply. for reliable operation, using 100 nf ceramic surface-mount capacitors for the pvdd and pgnd pins is recommended. the minimum of two capacitors are needed: one between pin 45/pin 46 (pvdd) and pin 47/pin48 (pgnd), the other between pin 39/ pin 40 (pvdd) and pin 37/pin 38 (pgnd). in addition, these
adau1592 rev. 0 | page 20 of 24 must be placed very close to the respective pins with direct connection. this is important for reliable and safe operation of the device. one additional 1 f capacitor in parallel to the 100 nf capacitor is also recommended. a bulk bypass capacitor of 470 f is also recommended to remove the low frequency ripple due to load current. similarly, one 100 nf capacitor is recommended between each dvdd/dgnd and avdd/agnd. these capacitors also must be placed close to their respective pins with direct connection. external protection for pvdd > 15 v as the pvdd supply voltage approaches 15 v and above, the available headroom with maximum pvdd reduces. as with any switching amplifier, the outputs swing to full rail and the amount of overshoots due to parasitic elements of the package/board would be significant. therefore, for reliable and safe operation it is recommended to add external protection circuits for applica- tions requiring supply voltages >15 v. the use of an rc snubber or a schottky diode on the outputs should be considered. the rc snubber should be connected between the outx+ and outx? pins for each channel. the typical recommended values are 10 and 680 pf. also, both of these components must be placed close to the output pins. for two channels, two resistors and two capacitors are needed. if schottky diodes are preferred, the diodes must be from each outx?/outx+ pin to pvdd/pgnd. so in total eight diodes are needed for two channels. the schottky diodes need to be placed close to the output pins to be effective. clock the adau1592 uses 24.576 mhz for the master clock, which is 512 f s ( f s = 48 khz). there are several options for providing the clock. option 1: using a uartz crystal a quartz crystal of 24.576 mhz frequency can be connected between the xti and xto pins using two load capacitors suitable for the crystal oscillation mode. option 2: using a ceramic resonator the adau1592 can also be used with ceramic resonators similar to crystal by using the xti and xto pins. option 3: using an external clock the adau1592 can be provided with an external clock of 24.576 mhz at the xti pin. the logic level for the clock input should be in the range of 3.3 v and 50% typical duty cycle. for systems using multiple adau1592s, it is recommended to use only one clock source if the adau1592s share the same power supply to prevent the beat frequencies of asynchronous clocks from appearing in the audio band. multiple adau1592s can be connected in a daisy chain by providing or generating a master clock from one adau1592 and subsequently connecting its xto output to the xti input of the next adau1592, and so on. however, using a simple logic buffer between the xto pin of one adau1592 to the xti pin of the next adau1592 is recommended. because the clock output is now buffered, it can be connected to the xti inputs of the remaining adau1592s, depending on the fanout capability of the logic buffer used.
adau1592 rev. 0 | page 21 of 24 applications information for applications with pvdd > 15 v, add components r1 and r2 = 10 typical, c5 and c6 = 680 pf typical, and d1 through d8 = crs 01/02. 06749-049 xti xto dgnd pgnd dvdd avdd agnd vref slc_th pvdd pvdd 3.3v outl? outr? outl+ mo/st test1 otw test3 outr+ test13 test12 ainr ainl test9 test8 mute stdn err 470f 100nf 100nf 100nf 1f 100nf 24.576mhz crystal or resonator test0 system logic microcontroller analog input right 100k ? r3 2.2f 4.7f 100nf analog input left 100k ? 2.2f d4 d3 pvdd r1 10 ? l2 l1 d1 d2 pvdd c1 c2 c5 680pf d7 d8 pvdd r2 10 ? l4 l3 d5 d6 pvdd c3 c4 c6 680pf adau1592 figure 49. typical stereo application circuit table 11. r3slicer threshold resistor v t v r3 1.1 24.9 1.17 20.5 1.24 16.5 1.32 12.4 table 12. output filter component values load impedance inductance l1 to l4 capacitance c1 to c4 f 4 10 1.5 6 15 1 8 22 0.68
adau1592 rev. 0 | page 22 of 24 06749-050 xti xto dgnd pgnd dvdd avdd agnd vref slc_th pvdd pvdd 3.3v outl? outr? outl+ test1 test0 otw test3 outr+ test13 test12 ainr ainl test9 test8 mute stdn err mo/st 100nf 100nf 100nf 1f 100nf 24.576mhz crystal or resonator system logic microcontroller analog input right 100k ? r3 2.2f 4.7f 100nf analog input left 100k ? 2.2f d4 d3 pvdd l2 l1 d1 d2 pvdd c1 c2 470f r1 10 ? c5 680pf adau1592 figure 50. typical mono application circuit for component values, refer to the stereo application circuit in figure 49.
adau1592 rev. 0 | page 23 of 24 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 51. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters compliant to jedec standards ms-026-abc 0.50 bsc lead pitch 0.27 0.22 0.17 7.20 7.00 sq 6.80 37 37 48 48 1 13 12 1 12 24 13 24 25 36 25 36 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw 7 3.5 0 0.15 0.05 1.20 max top view (pins down) bottom view (pins up) 5.10 sq exposed pad 9.20 9.00 sq 8.80 s e a t i n g p l a n e 0 . 7 5 0 . 6 0 0 . 4 5 1 . 0 0 r e f 042507-a v i e w a pin 1 figure 52. 48-lead thin quad flat package, exposed pad [tqfp_ep] (sv-48-5) dimensions shown in millimeters ordering guide model temperature range package description package option adau1592acpz 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 adau1592acpz-rl 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq], 13 tape and reel cp-48-1 adau1592acpz-rl7 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq], 7 tape and reel cp-48-1 adau1592asvz 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp_ep] sv-48-5 adau1592asvz-rl 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp_ep], 13 tape and reel sv-48-5 ADAU1592ASVZ-RL7 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp_ep], 7 tape and reel sv-48-5 1 z = rohs compliant part.
adau1592 rev. 0 | page 24 of 24 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06749-0-5/07(0)

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